Nowadays the demand of multi-standard applications has become a must for the worldwide user. In such a scenario, a wide range of contents can be provided by integrating onto the same device the support of different communication protocols, both satellite and terrestrial. Flexibility is then the keyword in the design of modern modems and particular attention must be paid to the implementation of the advanced channel coding techniques which represents the most challenging task in terms of computational complexity, speed and power consumption. Indeed, particularly for mobile devices, flexibility has to be combined with low complexity and power consumption.
The evolution of the mobile phone market represents a valuable example of this overwhelming trend. Born exclusively for voice services, it has quickly grown up embracing different data services such as Short-Message-Service (SMS), Multimedia-Messaging-Service and Wireless-Application-Protocol (WAP) internet connections. Nowadays, modern “smartphones” are designed to be capable of connecting to high speed cellular networks for mobile internet (3GPP-HSPA, 3GPP-LTE), high speed wireless local and metropolitan area networks for wireless internet connections (IEEE 802.11n, IEEE 802.16e) and satellite networks to receive broadcast video and multimedia contents (DVB-SH). This wide range of applications demands ever-increasing data rates and high reliability so as to guarantee an adequate Quality of Service (QoS). Channel coding is an effective method to improve the communication performances and, among the possible candidates, low-density parity-check (LDPC) and Turbo codes are regarded as excellent solutions for advanced forward error correction (FEC).
LDPC codes were first discovered by Gallager in 1960 but, despite the remarkable error correction performance, they were soon given up as their decoding complexity was too high with respect to the computation capabilities of the time. Recently, the impressive improvement of the micro-electronics technology having made the decoding complexity manageable, LDPC codes have become one of the most hot research topic in the field of communication systems. At the same time, the industrial attention to the LDPC codes has widely grown to such an extent that they have been included in several communication standards; namely the Digital Video Broadcasting Satellite Second generation DVB-S2, the second generation digital transmission system for cable and terrestrial systems DVB-C2 and DVB-T2, as well as IEEE 802.11n, IEEE 802.16e and IEEE 802.3an for new generation Ethernet connections.
Turbo codes were invented by Berrou in 1993 and have proved to be very effective forward error correcting codes featuring performance very close to the theoretical Shannon limit. The strength point of this invention was the introduction of the iterative decoding of the constituent convolutional codes. Nowadays, the Turbo code scheme is the preferred choice of many communication standards, such as, the 3rd generation partnership project standards (3GPP-UMTS, 3GPP-HSPA and 3GPP-LTE), the Digital video Broadcasting-Service to Handheld (DVB-SH), the Digital Video Broadcasting-return channel via satellite (DVB-RCS) and the IEEE 802.16e.
An advanced FEC channel decoder is often the most computational demanding block of the whole transceiver and consequently represents the bottleneck in terms of hardware-complexity, achievable data-rate and power consumption. Moreover the channel decoder must be compliant with all the communication standards specified by the particular device. In this sense, flexibility, i.e. the capability of supporting different communication standards with the minimum software/hardware utilization, represents the driving factor to keep complexity, latency and power consumption under control.
The most straightforward solution to attain flexibility is the design of one separated core for each channel decoding scheme (either LDPC or Turbo Codes or both) defined by all the communication standards to be supported. Although optimized in terms of data-rate and error correction performances, this approach is very demanding in terms of area and power consumption thus violating the strict budget of a mobile/portable device.
As an alternative way, it is possible to design two different cores implementing a Turbo and a LDPC flexible decoder architecture, respectively. Each core must be designed to be compliant with all the required standards, and commonalities between different code classes must be identified in order to efficiently share hardware resources and reduce the overall complexity. In this regard, Masera et al. proposes a flexible LDPC decoder compliant with IEEE 802.11n and IEEE 802.16e [1] and Lee et al. designed a flexible unified LDPC decoder architecture capable of supporting IEEE 802.11n, IEEE 802.16e and DVB-S2 [2]. As far as Turbo decoding is concerned, it is also worth mentioning the Flexible binary/duo-binary Turbo decoder architecture compliant with UMTS and IEEE 802.16e by Martina et al. [3] and the parallel radix-4 Turbo decoder for IEEE 802.16e and 3GPP-LTE by Kim et al. [4]. This last strategy allows a considerable reduction of the overall channel decoding platform complexity and power consumption; however it still requires two separate cores making it unsuitable for application where very strict area and power constraints are demanded, like in small mobile devices.
Application-Specific Instruction-set Processors (ASIP) allow the implementation of single-core flexible decoders. They are programmable circuits (processors) wherein a dedicated instruction-set is directly mapped on optimized hardware for improved performances. This optimized software/hardware configuration, tailored for the specific application, allows an high degree of flexibility with relatively low complexity. As an example, Alles at al. purpose the so-called FlexiChaP architecture [5], capable of supporting binary/duo-binary turbo codes as well as LDPC codes for IEEE 802.11n and IEEE 802.16e with a chip area of only 0.622 mm2 using a 65 nm CMOS technology. The key of such a design is the identification of common hardware resources that can be re-used among different decoding schemes and efficiently mapped into a software instruction. Another interesting ASIP channel decoding platform is proposed by Naessens et al. [6, 7] where the support of the IEEE 802.16e and IEEE 802.11n codes is achieved with a chip area of 0.96 mm2 using a 45 nm CMOS technology. The main drawback of this approach is the achievable data-rate (throughput) and the power consumption. Actually due to the very low hardware complexity, all the decoding steps must be performed in a time division manner. Consequently, in order to reduce the decoding time, the operating clock frequency is generally high with a considerable increase in the overall power consumption. As an example in [5] the operating clock frequency was pushed to 400 MHz and the attainable throughput was anyway not enough to fully support the IEEE 802.16e standard.
Joint minimization of hardware complexity and power consumption under demanding throughput constraints can only be achieved by an ASIC (Application Specific Integrated Circuit) implementation. Cavallaro et al. describes a preliminary ASIC flexible decoding architecture supporting both Turbo and LDPC codes [8]; however, such an architecture is not used to implement a Multi-Standard decoder but different ad-hoc single-standard solutions. Trofimenko et al. [9] disclose a “unified” decoder capable of supporting Turbo, LDPC and convolutional codes with a single core. However, this core is not optimized in terms of hardware complexity. Moreover, the critical issue of standard-dependent parallelization is not discussed. Three of the present inventors (Massimo Rovini, Giuseppe Gentile and Luca Fanucci) have disclosed an ASIC-implemented state-metric recursive unit, usable for both Turbo- and LDPC-decoding [10]. This unit, however, is only a component (albeit an important one) of a full flexible decoder.